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TSC80251G1D
Specification Update
1. Revision History
Date of revision
January 30, 1998 July 16, 1998 September 8, 1998
Version
A B C Creation with mask A5108 (included)
Description
Clarification of ERRATA C251G1D-20, Addition of ERRATA C251G1D-23 Re-organization with new ERRATA and new references
World Wide Web: http://www.temic-semi.de/ Product Hotline: C251@temic.fr
2. Preface
This document is an update to the specifications contained in Table 1. TSC80251G1 products implement a C251 architecture compliant to INTEL's MCS(R)251. Hence some of INTEL's specification update apply to TEMIC products. This includes INTEL's core stepping as outlined in Table 2.
Note: This document only applies to TEMIC's products and does not imply any product from INTEL has the same behavior. INTEL's Errata references are provided for information only when they are documented by Intel Corporation. Please refer to INTEL's documents if you intend to use INTEL's products in your system. Please refer to TEMIC's documents if you intend to use TEMIC's products in your systems.
Table 1. Affected Documents/Related Documents
Title
TSC80251G1D Datasheet TSC80251G1D Design Guide - October 1998 TSC80251 Programmer's Guide 1996
Reference
Rev. C - October 14, 1998 Rev. C - October 8, 1998 Rev. B - October 23, 1996
Table 2. TEMIC Products to INTEL's Core Version Reference
TEMIC Products A
TSC80251G1D-yyyyy TSC251G1Dzzzz-yyyyy Notes: yyyyy provides voltage range, speed, temperature range, packaging and conditioning options. zzzz provides the customer code for MaskROM. Please refer to Ordering Information in the Data Sheet for full information on the options.
INTEL's Core Version B C D
n n
Rev. C
- September 8, 1998
1
TSC80251G1D
3. Nomenclature
Errata are design defects or errors. These may cause the published (component, board, system) behavior to deviate from published specifications. Hardware and software designed to be used with any component, board, and system must consider all errata documented. Specification Changes are modifications to the current published specifications. These changes will be incorporated in any new release of the specification. Specification Clarifications describe a specification in greater detail or further highlight a specification's impact to a complex design situation. These clarifications will be incorporated in any new release of the specification. Documentation Changes include typos errors, or omissions from the current published specifications. These changes will be incorporated in any new release of the specifications (see Table 1).
Note: Errata from mask 5096 have been removed from this specification update. The Errata list of mask 5096 is available upon request for customers who have ordered mask ROM products with this version. The production ROMless and the new mask ROM derivatives are using mask 5108.
Table 3. Codes Used in Summary Table
Page (Page) Status Doc Fix No Fix Eval Document change or update will be implemented. This erratum is intended to be fixed in a future version of the component. There are no plans to fix this erratum. Plans to fix this erratum are under evaluation. Page location of item in this document.
2
Rev. C
- September 8, 1998
TSC80251G1D
4. Summary Tables of Changes
The following tables indicate the errata, specification changes, specification clarifications, or documentation changes which apply to TSC80251G1D derivatives. TEMIC may fix some of the errata in a future version of the component, and account for the other outstanding issues through documentation or specification changes as noted.
Table 4. Errata List
TEMIC Reference
C251G1D-01 C251G1D-02 C251G1D-03 C251G1D-04 C251G1D-05 C251G1D-06 C251G1D-07
INTEL Reference
N.A.
(1)
Page
4 5 5 6 6 7 7
Status
Fix Fix Fix Fix Fix Fix Fix
Errata
I2C Repeated Start Condition in Master Mode JBC Instruction Interrupt Handling Unit In-Process Stacking UART Start Bit Detection CCFx Clear Failure in Polling Mode CCFx Always Set when Match EWC-PCA Watchdog Reset
980009 N.A. N.A. N.A. N.A.
Note: 1. Not reported when releasing this specification update.
Table 5. Specification Changes
TEMIC Reference INTEL Reference Page Status
None
Specification Changes
Table 6. Specification Clarifications
TEMIC Reference INTEL Reference Page Status
None
Specification Clarifications
Table 7. Documentation Changes
TEMIC Reference INTEL Reference Page Status
None
Documentation Changes
Rev. C
- September 8, 1998
3
TSC80251G1D
5. Errata
Reference C251G1D-01 Problem
When the TSC80251G1D derivative is the I2C master, if STO flag is cleared and STA flag is set between two transfers and before the STOP condition of the first transfer is emitted, a repeated start condition is properly emitted but state F8h is set instead of 10h and SI flag is not set.
Erratum I2C Repeated Start Condition in Master Mode
Example
In the example hereafter, the second transfer is started before the stop condition appears on the bus. ORG ljmp MAIN: mov jnb mov clr jnb setb clr mov ... FF:0000h MAIN SSCON,#60h SI,$ SSDAT,#A0h SI SI,$ STO SI SSCON,#60h ; ; ; ; ; ; ; send start condition wait status 08h slave address send address wait status 20h or 18h stop condition send stop condition
; start an other transfer
Implication
After the problem has been triggered, the I2C bus is no longer available as it is fully occupied by the TSC80251G1D microcontroller emitting a start condition.
Workaround
To avoid problem, when starting a new transfer, STO flag should not be cleared, only STA flag should be set. The instruction mov Becomes setb STA ; start condition SSCON,#60h ; start an other transfer
Affected Products
All TSC80251G1D are affected.
4
Rev. C
- September 8, 1998
TSC80251G1D
Reference C251G1D-02 Problem
The JBC instruction uses a Read-Read-Modify-Write instruction. The write back is performed in any case, regardless of the value of the bit. A bit set by hardware between the first read and the second read is overwritten by the final write back.
Erratum JBC Instruction
Implication
Information is lost. This error affects the external interrupts flag (IE0 and IE1) of TCON register, the synchronous serial interrupt flag (SSI) of SSCON register and the keyboard interrupt flags (P1F.n, n=0..7) of P1F register.
Workaround
The workaround for this erratum is not to use the JBC instruction with the concerned flags.
Affected Products
All TSC80251G1D products are affected.
Reference C251G1D-03 Problem
Erratum Interrupt Handling Unit In-Process Stacking
After an interrupt has been successfully polled, an interrupt request is posted and the interrupt level is pushed on the interrupt in process stack which prevents any other interrupt occurring at a the same or at a lower level to be granted before the winning interrupt has returned. Then the interrupt request is waiting for the completion of the executing instruction to be processed. If a new interrupt has just been polled at an higher level when the pending interrupt request is being processed, the highest level interrupt will be pushed and granted but the previously waiting interrupt will be lost and its level will never be popped from the stack. A TRAP instruction leads to a priority interrupt processing occurring at the end of its execution. This leads to the same trouble if an interrupt request is pending during TRAP execution.
Note: The Hardware Breakpoint Trap used by emulators on the ICE bond-out is not affected by this trouble.
Implication
The interrupts at the lowest levels will be permanently disabled.
Workaround
Use only two priority levels and do not execute TRAP in sections where interrupts are enabled.
Note: NMI uses one independent priority level and cannot be disabled.
Affected Products
All TSC80251G1D products are affected.
Rev. C
- September 8, 1998
5
TSC80251G1D
Reference C251G1D-04 Problem
In asynchronous modes (1, 2 or 3), a START bit cannot be detected less than 1/16 bit time after a received STOP bit.
Erratum UART Start Bit Detection
Implication
The frames received by the TSC80251G1D derivatives are corrupted if there is only one STOP bit with no delay between two received characters.
Workaround
The workaround is depending on the application: D Have a delay between the characters transmitted to a TSC80251G1D derivative D Send more than one STOP bit (e.g. 1.5 or 2 stop bits) when communicating with a TSC80251G1D derivative Slightly increasing the TSC80251G1D receive baud rate might work but is not recommended. This will reduce the frequency excursion tolerance and may only be practicable when using low baud rates.
Affected Products
All TSC80251G1D are affected.
Reference C251G1D-05 Problem
Erratum CCFx Clear Failure in Polling Mode
When set by hardware, a CCFx flag (x= 0..4) is locked for one peripheral cycle (6 states). A clear instruction will not operate if it is writing to the flag during this period.
Implication
When a CCFx flag is tested and cleared in a polling loop, the clear instruction may fail clearing the flag. Then the flag can be found set several times with only one actual event. Considering the minimum interrupt processing latency, this cannot occur in Interrupt Mode.
Workaround
Wait or keep on clearing the flag at least 6 states after it has been set by hardware: loop_ccf0:... ... jnb jb clr ...
CCF0,loop_ccf0 CCF0,0 CCF0
; ; ; ;
polling loop until CCF0 is set jump always, more than 5 states delay clear instruction will work unless an new event occurred
Affected Products
All TSC80251G1D are affected. 6 Rev. C
- September 8, 1998
TSC80251G1D
Reference C251G1D-06 Problem
When the EWC Timer/Counter is not running, an alternate path is used to trigger the CCFx flag (x= 0..4) in the CCON register, irrespective of MATx value. This should not be the case when MATx is cleared, as highlighted in figure 5.3 of the referred Design Guide (see Table 1).
Erratum CCFx Always Set when Match
Implication
When the EWC Timer/Counter is not running, CCFx flag will be set when CH/CL are matching CCAPxH/CCAPxL and ECOMx is set, even if MATx is cleared.
Workaround
Avoid having CH/CL matching CCAPxH/CCAPxL if CR is cleared in CCON when ECOMx is set and MATx is cleared in CCAPMx.
Affected Products
All TSC80251G1D are affected.
Reference C251G1D-07 Problem
Erratum EWC-PCA Watchdog Reset
If CH/CL and CCAP4H/CCAP4L are matching when the software watchdog mode is configured on PCA module 4, an immediate reset occurs.
Example
In the example hereafter, the microcontroller resets immediately after setting WDTE. WDT_INIT: mov setb mov mov setb ... CCAPM4,#01001000b WDTE CCAP4L,#DELAY_L CCAP4H,#DELAY_H CR ; set ECOM4 and MAT4 ; enable WDT reset ; load comparison value ; start PCA timer
Implication
An internal reset is generated when configuring the PCA software watchdog (CH/CL and CCAP4H/CCAP4L are matching after reset).
Workaround
PCA counter and Channel comparison values must be set before PCA Channel 4 configuration. The above example becomes: WDT_INIT: mov mov mov setb setb ... CCAP4L,#DELAY_L CCAP4H,#DELAY_H CCAPM4,#01001000b WDTE CR ; load comparison value ; set ECOM4 and MAT4 ; enable WDT reset ; start PCA timer
Affected Products
All TSC80251G1D products are affected. Rev. C
- September 8, 1998
7
TSC80251G1D
6. Specification Changes
This section is intentionally left blank.
7. Specification Clarifications
This section is intentionally left blank.
8. Documentation Changes
This section is intentionally left blank.
8
Rev. C
- September 8, 1998

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